Forum stats game

For all your silly time-killing forum games.

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Box Boy
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Re: Forum stats game

Postby Box Boy » Mon Apr 27, 2009 9:14 pm UTC

Bartimaeus wrote:
Ansain wrote:
sje46 wrote:
CueBall wrote:
Vieto wrote:
Christophoros wrote:
poxic wrote:
Christophoros wrote:
Scelestus wrote:I tend not to embrace admitting illegal activity, online or in real life.
Signatures are for chumps.

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eaglef2
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Re: Forum stats game

Postby eaglef2 » Mon Apr 27, 2009 9:30 pm UTC

Bartimaeus wrote:
Ansain wrote:
sje46 wrote:
CueBall wrote:
Vieto wrote:
Christophoros wrote:
poxic wrote:
Christophoros wrote:
Scelestus wrote:I tend not to embrace admitting illegal activity, online or in real life.
"I am a four hundred-foot tall purple Platypus Bear with pink horns and silver wings."
-Azula, Avatar: The Last Airbender.

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Box Boy
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Re: Forum stats game

Postby Box Boy » Mon Apr 27, 2009 9:30 pm UTC

eaglef2 wrote:
Bartimaeus wrote:
Ansain wrote:
sje46 wrote:
CueBall wrote:
Vieto wrote:
Christophoros wrote:
poxic wrote:
Christophoros wrote:
Scelestus wrote:I tend not to embrace admitting illegal activity, online or in real life.
Signatures are for chumps.

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eaglef2
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Re: Forum stats game

Postby eaglef2 » Mon Apr 27, 2009 9:36 pm UTC

You are a really annoying by doing this
"I am a four hundred-foot tall purple Platypus Bear with pink horns and silver wings."
-Azula, Avatar: The Last Airbender.

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Box Boy
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Re: Forum stats game

Postby Box Boy » Mon Apr 27, 2009 9:38 pm UTC

eaglef2 wrote:You are a really annoying by doing this
Signatures are for chumps.

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Christophoros
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Re: Forum stats game

Postby Christophoros » Mon Apr 27, 2009 10:25 pm UTC

eaglef2 wrote:You are a really annoying by doing this
"Analogies in writing are like feathers on a snake."

"Exaggeration is a billion times worse than understatement."

Never Forget

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Ansain
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Re: Forum stats game

Postby Ansain » Mon Apr 27, 2009 10:29 pm UTC

eaglef2 wrote:You are a really annoying by doing this
Why put off till today what you could just as easily get done tomorrow?

I can mathematically prove that 1 equals 0!.

Parts a-x in my plan weren't that important anyways.

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Christophoros
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Re: Forum stats game

Postby Christophoros » Mon Apr 27, 2009 10:32 pm UTC

eaglef2 wrote:You are a really annoying by doing this
"Analogies in writing are like feathers on a snake."

"Exaggeration is a billion times worse than understatement."

Never Forget

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Re: Forum stats game

Postby Bartimaeus » Thu Apr 30, 2009 3:19 am UTC

SWINE FLU!!!!!

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DrStalker
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Re: Forum stats game

Postby DrStalker » Thu Apr 30, 2009 4:38 am UTC

SWINE FLU!!!!!
There are two types of people in the world: 1) those that can extrapolate from incomplete data.

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Re: Forum stats game

Postby mickyj300x » Thu Apr 30, 2009 5:34 am UTC

SWINE FLU!!!!!

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dedalus
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Re: Forum stats game

Postby dedalus » Thu Apr 30, 2009 6:51 am UTC

SWlNE FLU!!!1!
doogly wrote:Oh yea, obviously they wouldn't know Griffiths from Sakurai if I were throwing them at them.

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Re: Forum stats game

Postby thecamoninja » Thu Apr 30, 2009 6:52 pm UTC

Uh oh!
Be sure not to talk to any Mexicans!
Formerly known as Camoninja
- - -
Join /FG/ on Discord
Hardcore will never die, but you will.
- - -
Subsequently known as Lavender Manna

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Silvyr
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Re: Forum stats game

Postby Silvyr » Thu Apr 30, 2009 10:52 pm UTC

Also avoid toddlers!
Asmodieus wrote:You're a Cullen, Silvyr.

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Re: Forum stats game

Postby BigBoss » Thu Apr 30, 2009 11:13 pm UTC

And bacon!
You don't give up hope just because something's hopeless. You cover up your ears, and talk really loud.

Tampons could be used to stop a nosebleed! - Tillian

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Re: Forum stats game

Postby Silvyr » Thu Apr 30, 2009 11:24 pm UTC

And schools!
Asmodieus wrote:You're a Cullen, Silvyr.

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Re: Forum stats game

Postby tina-mat » Thu Apr 30, 2009 11:31 pm UTC

And don't forget to buy some Tamiflu and face masks on your way home.
Maybe a fool that neglects the lilies of FG.
poxic wrote:Y'know, tina-mat, I hadn't realised until today that your avatar was a stabby little girl. I just thought she was wanking her ponytails.
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Re: Forum stats game

Postby Silvyr » Thu Apr 30, 2009 11:34 pm UTC

Probably a good idea to ram your shopping cart into anyone with a sniffly nose while your at teh store.
Asmodieus wrote:You're a Cullen, Silvyr.

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Re: Forum stats game

Postby tina-mat » Thu Apr 30, 2009 11:39 pm UTC

Yeah. Arm yourself so you have some defense when it mutates into a zombie virus.

Zombie flu.
Maybe a fool that neglects the lilies of FG.
poxic wrote:Y'know, tina-mat, I hadn't realised until today that your avatar was a stabby little girl. I just thought she was wanking her ponytails.
Box Boy wrote:tina-mat is my lord and master.

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Bartimaeus
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Re: Forum stats game

Postby Bartimaeus » Fri May 01, 2009 12:10 am UTC

swine flu

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Esc
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Re: Forum stats game

Postby Esc » Fri Jun 12, 2009 11:06 pm UTC

No swine zombie influenza, please.
Spoiler:
Image Image Image Image
Silver2Falcon wrote: As soon as we see a space tourism company insulting their competitors in a crappy infomercial, Mars will be less than 20 years away.

‎‎‎

‎‎‎‎

Postby ‎‎‎ » Fri Jun 12, 2009 11:33 pm UTC

‎‎‎

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Tillian
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Postby Tillian » Fri Jun 12, 2009 11:36 pm UTC


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Re: Forum stats game

Postby mickyj300x » Sat Jun 13, 2009 1:56 am UTC


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Re: Forum stats game

Postby poxic » Sat Jun 13, 2009 2:26 am UTC

In everyone's life, at some time, our inner fire goes out. It is then burst into flame by an encounter with another human being. We should all be thankful for those people who rekindle the inner spirit.
- Albert Schweitzer, philosopher, physician, musician, Nobel laureate (14 Jan 1875-1965)

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Re: Forum stats game

Postby mickyj300x » Sat Jun 13, 2009 4:29 am UTC


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eaglef2
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Re: Forum stats game

Postby eaglef2 » Sat Jun 13, 2009 6:13 am UTC

screw you guys for subtly changing your posts...
"I am a four hundred-foot tall purple Platypus Bear with pink horns and silver wings."
-Azula, Avatar: The Last Airbender.

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dedalus
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Re: Forum stats game

Postby dedalus » Sat Jun 13, 2009 7:53 am UTC

screw you guys for subtly changing your posts.....
doogly wrote:Oh yea, obviously they wouldn't know Griffiths from Sakurai if I were throwing them at them.

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Re: Forum stats game

Postby poxic » Sat Jun 13, 2009 8:05 am UTC

screw you guys for subtly changing your posts......
In everyone's life, at some time, our inner fire goes out. It is then burst into flame by an encounter with another human being. We should all be thankful for those people who rekindle the inner spirit.
- Albert Schweitzer, philosopher, physician, musician, Nobel laureate (14 Jan 1875-1965)

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Tillian
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Re: Forum stats game

Postby Tillian » Sat Jun 13, 2009 10:11 am UTC

eaglef2 wrote:screw you guys for subtly changing your posts...
I just noticed today that you had edited your first post for me. That made me feel proud.

//tina
xkcd forum gamers' Discord chat: https://discord.gg/Q7QM5sH
heuristically_alone wrote:Tillian you are always in every single one of dreams,
usually driving an ice cream truck.
NOTE: This is not me. That's another guy.

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Re: Forum stats game

Postby Nith Azra » Sat Jun 13, 2009 5:58 pm UTC

eaglef2 wrote:screw you guys for subtly changing your posts...

I just noticed today that you had edited your first stop for me. That made me feel proud.

//tina
Mighty Jalapeno wrote:I wrote "moistly"... wierd.


::.._____..::ROYAL RAINBOW!!!::.._____..::

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dedalus
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Re: Forum stats game

Postby dedalus » Sun Jun 14, 2009 7:26 am UTC

eaglef2 wrote:
screw you guys for subtly changing your posts...

I just noticed today that you had edited your first stop for me. That made me feel proud.
Now I bet you're trying to see exactly what I changed.......
//tina
doogly wrote:Oh yea, obviously they wouldn't know Griffiths from Sakurai if I were throwing them at them.

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Re: Forum stats game

Postby Agent_Irons » Mon Jun 15, 2009 5:04 pm UTC

eaglef2 wrote:
screw you guys for subtly changing your posts...

I just noticed today that you had edited your first stop for me. That made me feel proud.
Now I bet you're trying to see exactly what I changed.......
\\tina

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eaglef2
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Re: Forum stats game

Postby eaglef2 » Mon Jun 15, 2009 6:55 pm UTC

it's the forward slashes
"I am a four hundred-foot tall purple Platypus Bear with pink horns and silver wings."
-Azula, Avatar: The Last Airbender.

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Tillan
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Re: Forum stats game

Postby Tillan » Mon Jun 15, 2009 9:25 pm UTC

The Pentium 4 processor, utilizing the Intel NetBurst micro-architecture, is a complete processor redesign
that delivers new technologies and capabilities while advancing many of the innovative features, such as
“out-of-order speculative execution” and “super-scalar execution,” introduced on prior Intel® microarchitecture
generations. Many of these innovations and advances were made possible with the
improvements in processor technology, transistor technology and circuit design, and they could not have
been implemented previously in high-volume, manufacturable solutions. The new technologies and
innovative features that are introduced in the Intel NetBurst micro-architecture are listed below:
Hyper-Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles
the pipeline depth, compared to the P6 micro-architecture, with a 20-stage pipeline. This technology
significantly increases processor performance and frequency scalability of the base micro-architecture.
400-MHz System Bus: Through a physical signaling scheme of quad pumping the data transfers over a 100-
MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers, the Pentium
4 processor supports the industry’s highest performance desktop system bus delivering a data rate of 3.2
Giga-Bytes per second (GB/s) in and out of the processor. This compares to 1.06 GB/s delivered on the
Pentium III processor’s 133-MHz system bus.
Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order
speculative execution engine that keeps the execution units busy. It does so by providing a very large
window of instructions from which the execution units can choose in order to get around stalls due to
instructions that are not ready to execute based on some unmet dependency (such as waiting for data to be
loaded from main memory). The NetBurst micro-architecture can have up to 126 instructions in this window
(in flight) versus the P6 micro-architecture’s much smaller window of 42 instructions.
The Advanced Dynamic Execution engine also delivers an enhanced branch prediction capability that allows
the processor to be more accurate in predicting program branches and has the net effect of reducing the
number of branch mispredictions by about 33% over the P6 micro-architecture’s branch prediction
capability. It does this by implementing a 4 Kilo Bytes (KB) branch target buffer in which to store more
detail on the history of past branches as well as implementing a more advanced branch prediction algorithm.
This enhanced branch prediction capability is one of the key design elements that helps to reduce the overall
sensitivity to branch misprediction penalty of the NetBurst micro-architecture.
Rapid Execution Engine: Through a combination of architectural, physical and circuit designs, the
Arithmetic Logic Units (ALUs) within the processor run at two times the frequency of the processor core.
This allows the ALUs to execute certain instructions in ½ a core clock and results in higher execution
throughput as well as reduced latency of execution.
Advanced Transfer Cache: The level 2 Advanced Transfer Cache is 256KB in size and delivers a much
higher data throughput channel between the level 2 cache and the processor core. The Advanced Transfer
Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, a 1.5-GHz
Pentium 4 processor could deliver a data transfer rate of 48GB/s (32 bytes x 1 (data transfer per clock) x 1.5
GHz = 48GB/s). This compares to a transfer rate of 16GB/s on the Pentium III processor 1 GHz and
contributes to the processor’s ability to keep the high-frequency execution units busy executing instructions
instead of sitting idle.
Execution Trace Cache: The Execution Trace Cache is an innovative way to implement a 1st level
instruction cache. It caches decoded IA-32 instructions (or micro-ops), thus removing the latency associated
with the instruction decoder from the main execution loops. In addition, the Execution Trace Cache stores
these micro-ops in the path of program execution flow, where the results of branches in the code are
integrated into the same cache line. This increases the instruction flow from the cache and makes better use
of the overall cache storage space (12K micro-ops) since the cache no longer stores instructions that are
branched over and never executed. The net result is a means to deliver a high volume of instructions to the
processor’s execution units and a reduction in the overall time required to recover from branches that have
been mispredicted.
Streaming SIMD Extensions 2 (SSE2): With the introduction of the SSE2 extensions, the NetBurst microarchitecture
now extends the SIMD capabilities of Intel® MMXTM technology and the SSE extensions by
Desktop Performance and Optimization for Pentium® 4 Processor
Page 7
adding 144 new instructions that perform 128-bit SIMD integer arithmetic operations and 128-bit SIMD
double-precision floating-point (FP) operations. These new instructions provide programmers with new
abilities to execute a particular program task on Pentium 4 processors with fewer instructions and in less
time. As a result using SSE2 extension can contribute significantly to an overall performance increase.
In addition, the Pentium 4 processor has implemenHAPPYCORE PORNOGRAPHYted a Hardware Prefetcher: The automatic hardware
prefetcher operates transparently without requiring programmer’s active intervention. It is triggered by
regular access patterns and helps predict future accesses, thereby overlapping memory latency with
computation. By enabling concurrency between memory accesses and computation, this maximizes the
computational benefit of higher Pentium 4 processor frequencies
1.2 Desktop Performance Expectations
The scalability of application performance with higher processor frequencies vary greatly across applications.
This is because different applications have different requirements and are coded differently. Application
code can be divided into the following categories: integer and basic office productivity applications versus
floating-point and multimedia applications. The instructions executed per clock achievable by these different
application categories varies greatly, and this variance is strongly affected by the number of branches that
application code typically takes and the predictability of these branches. The more branches taken with lower
predictability, the more opportunity to incorrectly predict the result of the branches, and hence the possibility
of performing nonproductive work.
Integer and basic office productivity applications, such as word and spreadsheet processing, tend to have
many branches in the code, thus reducing overall IPC capabilities. As a result, the associated branch penalties
and performance on these applications does not generally scale as well with frequency and are more resistant
to improvements in micro-architectural means, such as deeper pipelines. However, significantly raising the
performance level on these types of applications that run in basic, non-multitasking, environments does not
necessarily increase the user’s experience, because the processing power required by these types of basic
applications and environments tends to be satisfied by today’s higher end Pentium III processors.
Floating-point and multimedia applications tend to have branches that are very predictable, and thus naturally
have a higher average IPC capability. As a result, these types of applications generally scale very well with
frequency and are inclined to benefit greatly from deeper pipelines. In addition, the processing power
required by these applications tend to be unbounded: the more performance that is available, the better the
user’s experience.
The Pentium 4 processor shows immediate performance improvements across most existing software
available today, with performance levels varying depending on the application category type and the extent
that an application is optimized for the new micro-architecture.
An increase in frequency with previous micro-architectural generation products, such as the Pentium III
processor, generally did not yield performance increases equal to the frequency increases. The exact
efficiency of performance increase versus frequency (comparing a Pentium 4 processor at 1.5 GHz and a
Pentium III processor at 1GHz ) depends on individual application (see Figure 2), but in general you should
not expect to see a 50% increase in performance with a 50% increase in frequency (i.e. 100% efficiency of
converting frequency increase into performance gain in Figure 2). With a 40-50% increase in frequency, the
Pentium 4 processor was designed to yield in the range of a 20% gain on integer and a 20-70% gain on
floating-point/multi-media performance. (In workloads that include system-level activities, such as disk and
network accesses, the performance results depend less on processor performance. Therefore, the performance
scaling tends to be lower, SYSmark* 2000 is one such case.) As seen in Figure 2, the Pentium 4 processor
enables not only a large increase in frequency, but also demonstrates greater efficiency in translating this
frequency into performance gains, when compared to the Pentium III processor.

No copy-pasta quote tags people. Its in the rules.
Now work damnit! No, dont carry on posting here, you're a very busy person. work work work!!

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poxic
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Re: Forum stats game

Postby poxic » Mon Jun 15, 2009 9:34 pm UTC

The Pentium 4 processor, utilizing the Intel NetBurst micro-architecture, is a complete processor redesign
that delivers new technologies and capabilities while advancing many of the innovative features, such as
“out-of-order speculative execution” and “super-scalar execution,” introduced on prior Intel® microarchitecture
generations. Many of these innovations and advances were made possible with the
improvements in processor technology, transistor technology and circuit design, and they could not have
been implemented previously in high-volume, manufacturable solutions. The new technologies and
innovative features that are introduced in the Intel NetBurst micro-architecture are listed below:
Hyper-Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles
the pipeline depth, compared to the P6 micro-architecture, with a 20-stage pipeline. This technology
significantly increases processor performance and frequency scalability of the base micro-architecture.
400-MHz System Bus: Through a physical signaling scheme of quad pumping the data transfers over a 100-
MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers, the Pentium
4 processor supports the industry’s highest performance desktop system bus delivering a data rate of 3.2
Giga-Bytes per second (GB/s) in and out of the processor. This compares to 1.06 GB/s delivered on the
Pentium III processor’s 133-MHz system bus.
Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order
speculative execution engine that keeps the execution units busy. It does so by providing a very large
window of instructions from which the execution units can choose in order to get around stalls due to
instructions that are not ready to execute based on some unmet dependency (such as waiting for data to be
loaded from main memory). The NetBurst micro-architecture can have up to 126 instructions in this window
(in flight) versus the P6 micro-architecture’s much smaller window of 42 instructions.
The Advanced Dynamic Execution engine also delivers an enhanced branch prediction capability that allows
the processor to be more accurate in predicting program branches and has the net effect of reducing the
number of branch mispredictions by about 33% over the P6 micro-architecture’s branch prediction
capability. It does this by implementing a 4 Kilo Bytes (KB) branch target buffer in which to store more
detail on the history of past branches as well as implementing a more advanced branch prediction algorithm.
This enhanced branch prediction capability is one of the key design elements that helps to reduce the overall
sensitivity to branch misprediction penalty of the NetBurst micro-architecture.
Rapid Execution Engine: Through a combination of architectural, physical and circuit designs, the
Arithmetic Logic Units (ALUs) within the processor run at two times the frequency of the processor core.
This allows the ALUs to execute certain instructions in ½ a core clock and results in higher execution
throughput as well as reduced latency of execution.
Advanced Transfer Cache: The level 2 Advanced Transfer Cache is 256KB in size and delivers a much
higher data throughput channel between the level 2 cache and the processor core. The Advanced Transfer
Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, a 1.5-GHz
Pentium 4 processor could deliver a data transfer rate of 48GB/s (32 bytes x 1 (data transfer per clock) x 1.5
GHz = 48GB/s). This compares to a transfer rate of 16GB/s on the Pentium III processor 1 GHz and
contributes to the processor’s ability to keep the high-frequency execution units busy executing instructions
instead of sitting idle.
Execution Trace Cache: The Execution Trace Cache is an innovative way to implement a 1st level
instruction cache. It caches decoded IA-32 instructions (or micro-ops), thus removing the latency associated
with the instruction decoder from the main execution loops. In addition, the Execution Trace Cache stores
these micro-ops in the path of program execution flow, where the results of branches in the code are
integrated into the same cache line. This increases the instruction flow from the cache and makes better use
of the overall cache storage space (12K micro-ops) since the cache no longer stores instructions that are
branched over and never executed. The net result is a means to deliver a high volume of instructions to the
processor’s execution units and a reduction in the overall time required to recover from branches that have
been mispredicted.
Streaming SIMD Extensions 2 (SSE2): With the introduction of the SSE2 extensions, the NetBurst microarchitecture
now extends the SIMD capabilities of Intel® MMXTM technology and the SSE extensions by
Desktop Performance and Optimization for Pentium® 4 Processor
Page 7
adding 144 new instructions that perform 128-bit SIMD integer arithmetic operations and 128-bit SIMD
double-precision floating-point (FP) operations. These new instructions provide programmers with new
abilities to execute a particular program task on Pentium 4 processors with fewer instructions and in less
time. As a result using SSE2 extension can contribute significantly to an overall performance increase.
In addition, the Pentium 4 processor has implemenHAPPYCORE PORNOGRAPHYted a Hardware Prefetcher: The automatic hardware
prefetcher operates transparently without requiring programmer’s active intervention. It is triggered by
regular access patterns and helps predict future accesses, thereby overlapping memory latency with
computation. By enabling concurrency between memory accesses and computation, this maximizes the
computational benefit of higher Pentium 4 processor frequencies
1.2 Desktop Performance Expectations
The scalability of application performance with higher processor frequencies vary greatly across applications.
This is because different applications have different requirements and are coded differently. Application
code can be divided into the following categories: integer and basic office productivity applications versus
floating-point and multimedia applications. The instructions executed per clock achievable by these different
application categories varies greatly, and this variance is strongly affected by the number of branches that
application code typically takes and the predictability of these branches. The more branches taken with lower
predictability, the more opportunity to incorrectly predict the result of the branches, and hence the possibility
of performing nonproductive work.
Integer and basic office productivity applications, such as word and spreadsheet processing, tend to have
many branches in the code, thus reducing overall IPC capabilities. As a result, the associated branch penalties
and performance on these applications does not generally scale as well with frequency and are more resistant
to improvements in micro-architectural means, such as deeper pipelines. However, significantly raising the
performance level on these types of applications that run in basic, non-multitasking, environments does not
necessarily increase the user’s experience, because the processing power required by these types of basic
applications and environments tends to be satisfied by today’s higher end Pentium III processors.
Floating-point and multimedia applications tend to have branches that are very predictable, and thus naturally
have a higher average IPC capability. As a result, these types of applications generally scale very well with
frequency and are inclined to benefit greatly from deeper pipelines. In addition, the processing power
required by these applications tend to be unbounded: the more performance that is available, the better the
user’s experience.
The Pentium 4 processor shows immediate performance improvements across most existing software
available today, with performance levels varying depending on the application category type and the extent
that an application is optimized for the new micro-architecture.
An increase in frequency with previous micro-architectural generation products, such as the Pentium III
processor, generally did not yield performance increases equal to the frequency increases. The exact
efficiency of performance increase versus frequency (comparing a Pentium 4 processor at 1.5 GHz and a
Pentium III processor at 1GHz ) depends on individual application (see Figure 2), but in general you should
not expect to see a 50% increase in performance with a 50% increase in frequency (i.e. 100% efficiency of
converting frequency increase into performance gain in Figure 2). With a 40-50% increase in frequency, the
Pentium 4 processor was designed to yield in the range of a 20% gain on integer and a 20-70% gain on
floating-point/multi-media performance. (In workloads that include system-level activities, such as disk and
network accesses, the performance results depend less on processor performance. Therefore, the performance
scaling tends to be lower, SYSmark* 2000 is one such case.) As seen in Figure 2, the Pentium 4 processor
enables not only a large increase in frequency, but also demonstrates greater efficiency in translating this
frequency into performance gains, when compared to the Pentium III processor.

No copy-pasta quote tags people. Its in the rules.
In everyone's life, at some time, our inner fire goes out. It is then burst into flame by an encounter with another human being. We should all be thankful for those people who rekindle the inner spirit.
- Albert Schweitzer, philosopher, physician, musician, Nobel laureate (14 Jan 1875-1965)

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Tillan
Posts: 223
Joined: Sat Sep 20, 2008 1:36 pm UTC
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Re: Forum stats game

Postby Tillan » Mon Jun 15, 2009 9:37 pm UTC

The Pentium 4 processor, utilizing the Intel NetBurst micro-architecture, is a complete processor redesign
that delivers new technologies and capabilities while advancing many of the innovative features, such as
“out-of-order speculative execution” and “super-scalar execution,” introduced on prior Intel® microarchitecture
generations. Many of these innovations and advances were made possible with the
improvements in processor technology, transistor technology and circuit design, and they could not have
been implemented previously in high-volume, manufacturable solutions. The new technologies and
innovative features that are introduced in the Intel NetBurst micro-architecture are listed below:
Hyper-Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles
the pipeline depth, compared to the P6 micro-architecture, with a 20-stage pipeline. This technology
significantly increases processor performance and frequency scalability of the base micro-architecture.
400-MHz System Bus: Through a physical signaling scheme of quad pumping the data transfers over a 100-
MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers, the Pentium
4 processor supports the industry’s highest performance desktop system bus delivering a data rate of 3.2
Giga-Bytes per second (GB/s) in and out of the processor. This compares to 1.06 GB/s delivered on the
Pentium III processor’s 133-MHz system bus.
Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order
speculative execution engine that keeps the execution units busy. It does so by providing a very large
window of instructions from which the execution units can choose in order to get around stalls due to
instructions that are not ready to execute based on some unmet dependency (such as waiting for data to be
loaded from main memory). The NetBurst micro-architecture can have up to 126 instructions in this window
(in flight) versus the P6 micro-architecture’s much smaller window of 42 instructions.
The Advanced Dynamic Execution engine also delivers an enhanced branch prediction capability that allows
the processor to be more accurate in predicting program branches and has the net effect of reducing the
number of branch mispredictions by about 33% over the P6 micro-architecture’s branch prediction
capability. It does this by implementing a 4 Kilo Bytes (KB) branch target buffer in which to store more
detail on the history of past branches as well as implementing a more advanced branch prediction algorithm.
This enhanced branch prediction capability is one of the key design elements that helps to reduce the overall
sensitivity to branch misprediction penalty of the NetBurst micro-architecture.
Rapid Execution Engine: Through a combination of architectural, physical and circuit designs, the
Arithmetic Logic Units (ALUs) within the processor run at two times the frequency of the processor core.
This allows the ALUs to execute certain instructions in ½ a core clock and results in higher execution
throughput as well as reduced latency of execution.
Advanced Transfer Cache: The level 2 Advanced Transfer Cache is 256KB in size and delivers a much
higher data throughput channel between the level 2 cache and the processor core. The Advanced Transfer
Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, a 1.5-GHz
Pentium 4 processor could deliver a data transfer rate of 48GB/s (32 bytes x 1 (data transfer per clock) x 1.5
GHz = 48GB/s). This compares to a transfer rate of 16GB/s on the Pentium III processor 1 GHz and
contributes to the processor’s ability to keep the high-frequency execution units busy executing instructions
instead of sitting idle.
Execution Trace Cache: The Execution Trace Cache is an innovative way to implement a 1st level
instruction cache. It caches decoded IA-32 instructions (or micro-ops), thus removing the latency associated
with the instruction decoder from the main execution loops. In addition, the Execution Trace Cache stores
these micro-ops in the path of program execution flow, where the results of branches in the code are
integrated into the same cache line. This increases the instruction flow from the cache and makes better use
of the overall cache storage space (12K micro-ops) since the cache no longer stores instructions that are
branched over and never executed. The net result is a means to deliver a high volume of instructions to the
processor’s execution units and a reduction in the overall time required to recover from branches that have
been mispredicted.
Streaming SIMD Extensions 2 (SSE2): With the introduction of the SSE2 extensions, the NetBurst microarchitecture
now extends the SIMD capabilities of Intel® MMXTM technology and the SSE extensions by
Desktop Performance and Optimization for Pentium® 4 Processor
Page 7
adding 144 new instructions that perform 128-bit SIMD integer arithmetic operations and 128-bit SIMD
double-precision floating-point (FP) operations. These new instructions provide programmers with new
abilities to execute a particular program task on Pentium 4 processors with fewer instructions and in less
time. As a result using SSE2 extension can contribute significantly to an overall performance increase.
In addition, the Pentium 4 processor has implemenHAPPYCORE PORNOGRAPHYted a Hardware Prefetcher: The automatic hardware
prefetcher operates transparently without requiring programmer’s active intervention. It is triggered by
regular access patterns and helps predict future accesses, thereby overlapping memory latency with
computation. By enabling concurrency between memory accesses and computation, this maximizes the
computational benefit of higher Pentium 4 processor frequencies
1.2 Desktop Performance Expectations
The scalability of application performance with higher processor frequencies vary greatly across applications.
This is because different applications have different requirements and are coded differently. Application
code can be divided into the following categories: integer and basic office productivity applications versus
floating-point and multimedia applications. The instructions executed per clock achievable by these different
application categories varies greatly, and this variance is strongly affected by the number of branches that
application code typically takes and the predictability of these branches. The more branches taken with lower
predictability, the more opportunity to incorrectly predict the result of the branches, and hence the possibility
of performing nonproductive work.
Integer and basic office productivity applications, such as word and spreadsheet processing, tend to have
many branches in the code, thus reducing overall IPC capabilities. As a result, the associated branch penalties
and performance on these applications does not generally scale as well with frequency and are more resistant
to improvements in micro-architectural means, such as deeper pipelines. However, significantly raising the
performance level on these types of applications that run in basic, non-multitasking, environments does not
necessarily increase the user’s experience, because the processing power required by these types of basic
applications and environments tends to be satisfied by today’s higher end Pentium III processors.
Floating-point and multimedia applications tend to have branches that are very predictable, and thus naturally
have a higher average IPC capability. As a result, these types of applications generally scale very well with
frequency and are inclined to benefit greatly from deeper pipelines. In addition, the processing power
required by these applications tend to be unbounded: the more performance that is available, the better the
user’s experience.
The Pentium 4 processor shows immediate performance improvements across most existing software
available today, with performance levels varying depending on the application category type and the extent
that an application is optimized for the new micro-architecture.
An increase in frequency with previous micro-architectural generation products, such as the Pentium III
processor, generally did not yield performance increases equal to the frequency increases. The exact
efficiency of performance increase versus frequency (comparing a Pentium 4 processor at 1.5 GHz and a
Pentium III processor at 1GHz ) depends on individual application (see Figure 2), but in general you should
not expect to see a 50% increase in performance with a 50% increase in frequency (i.e. 100% efficiency of
converting frequency increase into performance gain in Figure 2). With a 40-50% increase in frequency, the
Pentium 4 processor was designed to yield in the range of a 20% gain on integer and a 20-70% gain on
floating-point/multi-media performance. (In workloads that include system-level activities, such as disk and
network accesses, the performance results depend less on processor performance. Therefore, the performance
scaling tends to be lower, SYSmark* 2000 is one such case.) As seen in Figure 2, the Pentium 4 processor
enables not only a large increase in frequency, but also demonstrates greater efficiency in translating this
frequency into performance gains, when compared to the Pentium III processor.

No copy-pasta quote tags people. Its in the rules.
Now work damnit! No, dont carry on posting here, you're a very busy person. work work work!!

User avatar
poxic
Eloquently Prismatic
Posts: 4751
Joined: Sat Jun 07, 2008 3:28 am UTC
Location: Left coast of Canada

Re: Forum stats game

Postby poxic » Mon Jun 15, 2009 9:40 pm UTC

The Pentium 4 processor, utilizing the Intel NetBurst micro-architecture, is a complete processor redesign
that delivers new technologies and capabilities while advancing many of the innovative features, such as
“out-of-order speculative execution” and “super-scalar execution,” introduced on prior Intel® microarchitecture
generations. Many of these innovations and advances were made possible with the
improvements in processor technology, transistor technology and circuit design, and they could not have
been implemented previously in high-volume, manufacturable solutions. The new technologies and
innovative features that are introduced in the Intel NetBurst micro-architecture are listed below:
Hyper-Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles
the pipeline depth, compared to the P6 micro-architecture, with a 20-stage pipeline. This technology
significantly increases processor performance and frequency scalability of the base micro-architecture.
400-MHz System Bus: Through a physical signaling scheme of quad pumping the data transfers over a 100-
MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers, the Pentium
4 processor supports the industry’s highest performance desktop system bus delivering a data rate of 3.2
Giga-Bytes per second (GB/s) in and out of the processor. This compares to 1.06 GB/s delivered on the
Pentium III processor’s 133-MHz system bus.
Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order
speculative execution engine that keeps the execution units busy. It does so by providing a very large
window of instructions from which the execution units can choose in order to get around stalls due to
instructions that are not ready to execute based on some unmet dependency (such as waiting for data to be
loaded from main memory). The NetBurst micro-architecture can have up to 126 instructions in this window
(in flight) versus the P6 micro-architecture’s much smaller window of 42 instructions.
The Advanced Dynamic Execution engine also delivers an enhanced branch prediction capability that allows
the processor to be more accurate in predicting program branches and has the net effect of reducing the
number of branch mispredictions by about 33% over the P6 micro-architecture’s branch prediction
capability. It does this by implementing a 4 Kilo Bytes (KB) branch target buffer in which to store more
detail on the history of past branches as well as implementing a more advanced branch prediction algorithm.
This enhanced branch prediction capability is one of the key design elements that helps to reduce the overall
sensitivity to branch misprediction penalty of the NetBurst micro-architecture.
Rapid Execution Engine: Through a combination of architectural, physical and circuit designs, the
Arithmetic Logic Units (ALUs) within the processor run at two times the frequency of the processor core.
This allows the ALUs to execute certain instructions in ½ a core clock and results in higher execution
throughput as well as reduced latency of execution.
Advanced Transfer Cache: The level 2 Advanced Transfer Cache is 256KB in size and delivers a much
higher data throughput channel between the level 2 cache and the processor core. The Advanced Transfer
Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, a 1.5-GHz
Pentium 4 processor could deliver a data transfer rate of 48GB/s (32 bytes x 1 (data transfer per clock) x 1.5
GHz = 48GB/s). This compares to a transfer rate of 16GB/s on the Pentium III processor 1 GHz and
contributes to the processor’s ability to keep the high-frequency execution units busy executing instructions
instead of sitting idle.
Execution Trace Cache: The Execution Trace Cache is an innovative way to implement a 1st level
instruction cache. It caches decoded IA-32 instructions (or micro-ops), thus removing the latency associated
with the instruction decoder from the main execution loops. In addition, the Execution Trace Cache stores
these micro-ops in the path of program execution flow, where the results of branches in the code are
integrated into the same cache line. This increases the instruction flow from the cache and makes better use
of the overall cache storage space (12K micro-ops) since the cache no longer stores instructions that are
branched over and never executed. The net result is a means to deliver a high volume of instructions to the
processor’s execution units and a reduction in the overall time required to recover from branches that have
been mispredicted.
Streaming SIMD Extensions 2 (SSE2): With the introduction of the SSE2 extensions, the NetBurst microarchitecture
now extends the SIMD capabilities of Intel® MMXTM technology and the SSE extensions by
Desktop Performance and Optimization for Pentium® 4 Processor
Page 7
adding 144 new instructions that perform 128-bit SIMD integer arithmetic operations and 128-bit SIMD
double-precision floating-point (FP) operations. These new instructions provide programmers with new
abilities to execute a particular program task on Pentium 4 processors with fewer instructions and in less
time. As a result using SSE2 extension can contribute significantly to an overall performance increase.
In addition, the Pentium 4 processor has implemenHAPPYCORE PORNOGRAPHYted a Hardware Prefetcher: The automatic hardware
prefetcher operates transparently without requiring programmer’s active intervention. It is triggered by
regular access patterns and helps predict future accesses, thereby overlapping memory latency with
computation. By enabling concurrency between memory accesses and computation, this maximizes the
computational benefit of higher Pentium 4 processor frequencies
1.2 Desktop Performance Expectations
The scalability of application performance with higher processor frequencies vary greatly across applications.
This is because different applications have different requirements and are coded differently. Application
code can be divided into the following categories: integer and basic office productivity applications versus
floating-point and multimedia applications. The instructions executed per clock achievable by these different
application categories varies greatly, and this variance is strongly affected by the number of branches that
application code typically takes and the predictability of these branches. The more branches taken with lower
predictability, the more opportunity to incorrectly predict the result of the branches, and hence the possibility
of performing nonproductive work.
Integer and basic office productivity applications, such as word and spreadsheet processing, tend to have
many branches in the code, thus reducing overall IPC capabilities. As a result, the associated branch penalties
and performance on these applications does not generally scale as well with frequency and are more resistant
to improvements in micro-architectural means, such as deeper pipelines. However, significantly raising the
performance level on these types of applications that run in basic, non-multitasking, environments does not
necessarily increase the user’s experience, because the processing power required by these types of basic
applications and environments tends to be satisfied by today’s higher end Pentium III processors.
Floating-point and multimedia applications tend to have branches that are very predictable, and thus naturally
have a higher average IPC capability. As a result, these types of applications generally scale very well with
frequency and are inclined to benefit greatly from deeper pipelines. In addition, the processing power
required by these applications tend to be unbounded: the more performance that is available, the better the
user’s experience.
The Pentium 4 processor shows immediate performance improvements across most existing software
available today, with performance levels varying depending on the application category type and the extent
that an application is optimized for the new micro-architecture.
An increase in frequency with previous micro-architectural generation products, such as the Pentium III
processor, generally did not yield performance increases equal to the frequency increases. The exact
efficiency of performance increase versus frequency (comparing a Pentium 4 processor at 1.5 GHz and a
Pentium III processor at 1GHz ) depends on individual application (see Figure 2), but in general you should
not expect to see a 50% increase in performance with a 50% increase in frequency (i.e. 100% efficiency of
converting frequency increase into performance gain in Figure 2). With a 40-50% increase in frequency, the
Pentium 4 processor was designed to yield in the range of a 20% gain on integer and a 20-70% gain on
floating-point/multi-media performance. (In workloads that include system-level activities, such as disk and
network accesses, the performance results depend less on processor performance. Therefore, the performance
scaling tends to be lower, SYSmark* 2000 is one such case.) As seen in Figure 2, the Pentium 4 processor
enables not only a large increase in frequency, but also demonstrates greater efficiency in translating this
frequency into performance gains, when compared to the Pentium III processor.

No copy-pasta quote tags people. Its in the rules.
In everyone's life, at some time, our inner fire goes out. It is then burst into flame by an encounter with another human being. We should all be thankful for those people who rekindle the inner spirit.
- Albert Schweitzer, philosopher, physician, musician, Nobel laureate (14 Jan 1875-1965)

User avatar
Tillan
Posts: 223
Joined: Sat Sep 20, 2008 1:36 pm UTC
Location: Coffee
Contact:

Re: Forum stats game

Postby Tillan » Mon Jun 15, 2009 9:41 pm UTC

The Pentium 4 processor, utilizing the Intel NetBurst micro-architecture, is a complete processor redesign
that delivers new technologies and capabilities while advancing many of the innovative features, such as
“out-of-order speculative execution” and “super-scalar execution,” introduced on prior Intel® microarchitecture
generations. Many of these innovations and advances were made possible with the
improvements in processor technology, transistor technology and circuit design, and they could not have
been implemented previously in high-volume, manufacturable solutions. The new technologies and
innovative features that are introduced in the Intel NetBurst micro-architecture are listed below:
Hyper-Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles
the pipeline depth, compared to the P6 micro-architecture, with a 20-stage pipeline. This technology
significantly increases processor performance and frequency scalability of the base micro-architecture.
400-MHz System Bus: Through a physical signaling scheme of quad pumping the data transfers over a 100-
MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers, the Pentium
4 processor supports the industry’s highest performance desktop system bus delivering a data rate of 3.2
Giga-Bytes per second (GB/s) in and out of the processor. This compares to 1.06 GB/s delivered on the
Pentium III processor’s 133-MHz system bus.
Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order
speculative execution engine that keeps the execution units busy. It does so by providing a very large
window of instructions from which the execution units can choose in order to get around stalls due to
instructions that are not ready to execute based on some unmet dependency (such as waiting for data to be
loaded from main memory). The NetBurst micro-architecture can have up to 126 instructions in this window
(in flight) versus the P6 micro-architecture’s much smaller window of 42 instructions.
The Advanced Dynamic Execution engine also delivers an enhanced branch prediction capability that allows
the processor to be more accurate in predicting program branches and has the net effect of reducing the
number of branch mispredictions by about 33% over the P6 micro-architecture’s branch prediction
capability. It does this by implementing a 4 Kilo Bytes (KB) branch target buffer in which to store more
detail on the history of past branches as well as implementing a more advanced branch prediction algorithm.
This enhanced branch prediction capability is one of the key design elements that helps to reduce the overall
sensitivity to branch misprediction penalty of the NetBurst micro-architecture.
Rapid Execution Engine: Through a combination of architectural, physical and circuit designs, the
Arithmetic Logic Units (ALUs) within the processor run at two times the frequency of the processor core.
This allows the ALUs to execute certain instructions in ½ a core clock and results in higher execution
throughput as well as reduced latency of execution.
Advanced Transfer Cache: The level Advanced Transfer Cache is 256KB in size and delivers a much
higher data throughput channel between the level 2 cache and the processor core. The Advanced Transfer
Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, a 1.5-GHz
Pentium 4 processor could deliver a data transfer rate of 48GB/s (32 bytes x 1 (data transfer per clock) x 1.5
GHz = 48GB/s). This compares to a transfer rate of 16GB/s on the Pentium III processor 1 GHz and
contributes to the processor’s ability to keep the high-frequency execution units busy executing instructions
instead of sitting idle.
Execution Trace Cache: The Execution Trace Cache is an innovative way to implement a 1st level
instruction cache. It caches decoded IA-32 instructions (or micro-ops), thus removing the latency associated
with the instruction decoder from the main execution loops. In addition, the Execution Trace Cache stores
these micro-ops in the path of program execution flow, where the results of branches in the code are
integrated into the same cache line. This increases the instruction flow from the cache and makes better use
of the overall cache storage space (12K micro-ops) since the cache no longer stores instructions that are
branched over and never executed. The net result is a means to deliver a high volume of instructions to the
processor’s execution units and a reduction in the overall time required to recover from branches that have
been mispredicted.
Streaming SIMD Extensions 2 (SSE2): With the introduction of the SSE2 extensions, the NetBurst microarchitecture
now extends the SIMD capabilities of Intel® MMXTM technology and the SSE extensions by
Desktop Performance and Optimization for Pentium® 4 Processor
Page 7
adding 144 new instructions that perform 128-bit SIMD integer arithmetic operations and 128-bit SIMD
double-precision floating-point (FP) operations. These new instructions provide programmers with new
abilities to execute a particular program task on Pentium 4 processors with fewer instructions and in less
time. As a result using SSE2 extension can contribute significantly to an overall performance increase.
In addition, the Pentium 4 processor has implemenHAPPYCORE PORNOGRAPHYted a Hardware Prefetcher: The automatic hardware
prefetcher operates transparently without requiring programmer’s active intervention. It is triggered by
regular access patterns and helps predict future accesses, thereby overlapping memory latency with
computation. By enabling concurrency between memory accesses and computation, this maximizes the
computational benefit of higher Pentium 4 processor frequencies
1.2 Desktop Performance Expectations
The scalability of application performance with higher processor frequencies vary greatly across applications.
This is because different applications have different requirements and are coded differently. Application
code can be divided into the following categories: integer and basic office productivity applications versus
floating-point and multimedia applications. The instructions executed per clock achievable by these different
application categories varies greatly, and this variance is strongly affected by the number of branches that
application code typically takes and the predictability of these branches. The more branches taken with lower
predictability, the more opportunity to incorrectly predict the result of the branches, and hence the possibility
of performing nonproductive work.
Integer and basic office productivity applications, such as word and spreadsheet processing, tend to have
many branches in the code, thus reducing overall IPC capabilities. As a result, the associated branch penalties
and performance on these applications does not generally scale as well with frequency and are more resistant
to improvements in micro-architectural means, such as deeper pipelines. However, significantly raising the
performance level on these types of applications that run in basic, non-multitasking, environments does not
necessarily increase the user’s experience, because the processing power required by these types of basic
applications and environments tends to be satisfied by today’s higher end Pentium III processors.
Floating-point and multimedia applications tend to have branches that are very predictable, and thus naturally
have a higher average IPC capability. As a result, these types of applications generally scale very well with
frequency and are inclined to benefit greatly from deeper pipelines. In addition, the processing power
required by these applications tend to be unbounded: the more performance that is available, the better the
user’s experience.
The Pentium 4 processor shows immediate performance improvements across most existing software
available today, with performance levels varying depending on the application category type and the extent
that an application is optimized for the new micro-architecture.
An increase in frequency with previous micro-architectural generation products, such as the Pentium III
processor, generally did not yield performance increases equal to the frequency increases. The exact
efficiency of performance increase versus frequency (comparing a Pentium 4 processor at 1.5 GHz and a
Pentium III processor at 1GHz ) depends on individual application (see Figure 2), but in general you should
not expect to see a 50% increase in performance with a 50% increase in frequency (i.e. 100% efficiency of
converting frequency increase into performance gain in Figure 2). With a 40-50% increase in frequency, the
Pentium 4 processor was designed to yield in the range of a 20% gain on integer and a 20-70% gain on
floating-point/multi-media performance. (In workloads that include system-level activities, such as disk and
network accesses, the performance results depend less on processor performance. Therefore, the performance
scaling tends to be lower, SYSmark* 2000 is one such case.) As seen in Figure 2, the Pentium 4 processor
enables not only a large increase in frequency, but also demonstrates greater efficiency in translating this
frequency into performance gains, when compared to the Pentium III processor.

No copy-pasta quote tags people. Its in the rules.
Now work damnit! No, dont carry on posting here, you're a very busy person. work work work!!

User avatar
poxic
Eloquently Prismatic
Posts: 4751
Joined: Sat Jun 07, 2008 3:28 am UTC
Location: Left coast of Canada

Re: Forum stats game

Postby poxic » Mon Jun 15, 2009 9:43 pm UTC

The Pentium 4 processor, utilizing the Intel NetBurst micro-architecture, is a complete processor redesign
that delivers new technologies and capabilities while advancing many of the innovative features, such as
“out-of-order speculative execution” and “super-scalar execution,” introduced on prior Intel® microarchitecture
generations. Many of these innovations and advances were made possible with the
improvements in processor technology, transistor technology and circuit design, and they could not have
been implemented previously in high-volume, manufacturable solutions. The new technologies and
innovative features that are introduced in the Intel NetBurst micro-architecture are listed below:
Hyper-Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles
the pipeline depth, compared to the P6 micro-architecture, with a 20-stage pipeline. This technology
significantly increases processor performance and frequency scalability of the base micro-architecture.
400-MHz System Bus: Through a physical signaling scheme of quad pumping the data transfers over a 100-
MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers, the Pentium
4 processor supports the industry’s highest performance desktop system bus delivering a data rate of 3.2
Giga-Bytes per second (GB/s) in and out of the processor. This compares to 1.06 GB/s delivered on the
Pentium III processor’s 133-MHz system bus.
Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order
speculative execution engine that keeps the execution units busy. It does so by providing a very large
window of instructions from which the execution units can choose in order to get around stalls due to
instructions that are not ready to execute based on some unmet dependency (such as waiting for data to be
loaded from main memory). The NetBurst micro-architecture can have up to 126 instructions in this window
(in flight) versus the P6 micro-architecture’s much smaller window of 42 instructions.
The Advanced Dynamic Execution engine also delivers an enhanced branch prediction capability that allows
the processor to be more accurate in predicting program branches and has the net effect of reducing the
number of branch mispredictions by about 33% over the P6 micro-architecture’s branch prediction
capability. It does this by implementing a 4 Kilo Bytes (KB) branch target buffer in which to store more
detail on the history of past branches as well as implementing a more advanced branch prediction algorithm.
This enhanced branch prediction capability is one of the key design elements that helps to reduce the overall
sensitivity to branch misprediction penalty of the NetBurst micro-architecture.
Rapid Execution Engine: Through a combination of architectural, physical and circuit designs, the
Arithmetic Logic Units (ALUs) within the processor run at two times the frequency of the processor core.
This allows the ALUs to execute certain instructions in ½ a core clock and results in higher execution
throughput as well as reduced latency of execution.
Advanced Transfer Cache: The level 2 Advanced Transfer Cache is 256kB in size and delivers a much
higher data throughput channel between the level 2 cache and the processor core. The Advanced Transfer
Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, a 1.5-GHz
Pentium 4 processor could deliver a data transfer rate of 48GB/s (32 bytes x 1 (data transfer per clock) x 1.5
GHz = 48GB/s). This compares to a transfer rate of 16GB/s on the Pentium III processor 1 GHz and
contributes to the processor’s ability to keep the high-frequency execution units busy executing instructions
instead of sitting idle.
Execution Trace Cache: The Execution Trace Cache is an innovative way to implement a 1st level
instruction cache. It caches decoded IA-32 instructions (or micro-ops), thus removing the latency associated
with the instruction decoder from the main execution loops. In addition, the Execution Trace Cache stores
these micro-ops in the path of program execution flow, where the results of branches in the code are
integrated into the same cache line. This increases the instruction flow from the cache and makes better use
of the overall cache storage space (12K micro-ops) since the cache no longer stores instructions that are
branched over and never executed. The net result is a means to deliver a high volume of instructions to the
processor’s execution units and a reduction in the overall time required to recover from branches that have
been mispredicted.
Streaming SIMD Extensions 2 (SSE2): With the introduction of the SSE2 extensions, the NetBurst microarchitecture
now extends the SIMD capabilities of Intel® MMXTM technology and the SSE extensions by
Desktop Performance and Optimization for Pentium® 4 Processor
Page 7
adding 144 new instructions that perform 128-bit SIMD integer arithmetic operations and 128-bit SIMD
double-precision floating-point (FP) operations. These new instructions provide programmers with new
abilities to execute a particular program task on Pentium 4 processors with fewer instructions and in less
time. As a result using SSE2 extension can contribute significantly to an overall performance increase.
In addition, the Pentium 4 processor has implemenHAPPYCORE PORNOGRAPHYted a Hardware Prefetcher: The automatic hardware
prefetcher operates transparently without requiring programmer’s active intervention. It is triggered by
regular access patterns and helps predict future accesses, thereby overlapping memory latency with
computation. By enabling concurrency between memory accesses and computation, this maximizes the
computational benefit of higher Pentium 4 processor frequencies
1.2 Desktop Performance Expectations
The scalability of application performance with higher processor frequencies vary greatly across applications.
This is because different applications have different requirements and are coded differently. Application
code can be divided into the following categories: integer and basic office productivity applications versus
floating-point and multimedia applications. The instructions executed per clock achievable by these different
application categories varies greatly, and this variance is strongly affected by the number of branches that
application code typically takes and the predictability of these branches. The more branches taken with lower
predictability, the more opportunity to incorrectly predict the result of the branches, and hence the possibility
of performing nonproductive work.
Integer and basic office productivity applications, such as word and spreadsheet processing, tend to have
many branches in the code, thus reducing overall IPC capabilities. As a result, the associated branch penalties
and performance on these applications does not generally scale as well with frequency and are more resistant
to improvements in micro-architectural means, such as deeper pipelines. However, significantly raising the
performance level on these types of applications that run in basic, non-multitasking, environments does not
necessarily increase the user’s experience, because the processing power required by these types of basic
applications and environments tends to be satisfied by today’s higher end Pentium III processors.
Floating-point and multimedia applications tend to have branches that are very predictable, and thus naturally
have a higher average IPC capability. As a result, these types of applications generally scale very well with
frequency and are inclined to benefit greatly from deeper pipelines. In addition, the processing power
required by these applications tend to be unbounded: the more performance that is available, the better the
user’s experience.
The Pentium 4 processor shows immediate performance improvements across most existing software
available today, with performance levels varying depending on the application category type and the extent
that an application is optimized for the new micro-architecture.
An increase in frequency with previous micro-architectural generation products, such as the Pentium III
processor, generally did not yield performance increases equal to the frequency increases. The exact
efficiency of performance increase versus frequency (comparing a Pentium 4 processor at 1.5 GHz and a
Pentium III processor at 1GHz ) depends on individual application (see Figure 2), but in general you should
not expect to see a 50% increase in performance with a 50% increase in frequency (i.e. 100% efficiency of
converting frequency increase into performance gain in Figure 2). With a 40-50% increase in frequency, the
Pentium 4 processor was designed to yield in the range of a 20% gain on integer and a 20-70% gain on
floating-point/multi-media performance. (In workloads that include system-level activities, such as disk and
network accesses, the performance results depend less on processor performance. Therefore, the performance
scaling tends to be lower, SYSmark* 2000 is one such case.) As seen in Figure 2, the Pentium 4 processor
enables not only a large increase in frequency, but also demonstrates greater efficiency in translating this
frequency into performance gains, when compared to the Pentium III processor.

No copy-pasta quote tags people. Its in the rules.
In everyone's life, at some time, our inner fire goes out. It is then burst into flame by an encounter with another human being. We should all be thankful for those people who rekindle the inner spirit.
- Albert Schweitzer, philosopher, physician, musician, Nobel laureate (14 Jan 1875-1965)


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